R8C2G datasheet(73/344 Pages) RENESAS

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R8C/2G Group

7. Comparator

Rev.1.00

Apr 04, 2008

Page 53 of 318

REJ09B0387-0100

Figure 7.8

VCAC Register

Figure 7.9

BGRCR Register

Voltage Monitor Circuit Edge Select Register

Symbol

Address

After Reset

VCAC

003Dh

00h

Bit Symbol

Bit Name

Function

NOTES:

b7 b6 b5 b4

b3 b2 b1

—

(b0)

—

VCAC1

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Comparator 1 circuit edge select

bit(1)

0: One edge

1: Both edges

VCAC2

Comparator 2 circuit edge select

bit(2)

0: One edge

1: Both edges

The VW2C7 bit in the VW2C register is enabled w hen the VCAC2 bit is set to 0 (one edge). Set the VW2C7 bit after

setting the VCAC2 bit to 0.

The VW1C7 bit in the VW1C register is enabled w hen the VCAC1 bit is set to 0 (one edge). Set the VW1C7 bit after

setting the VCAC1 bit to 0.

—

(b7-b3)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

BGR Control Register(1)

Symbol

Address

After Reset

BGRCR

003Eh

00h

Bit Symbol

Bit Name

Function

NOTES:

2. When the BGRCR0 bit is set to 1 (disabled), the accuracy/precision of the follow ing is not guaranteed:

• Internal reference voltage for comparator 1 and comparator 2

• Detection voltage for voltage detection circuit 0 to voltage detection circuit 2

• Oscillation frequency of the high-speed on-chip oscillator

Use these functions w hile the BGRCR0 bit is set to 0 (enabled).

To set the BGRCR0 bit to 1 (disabled), first disable voltage detection circuits 0 to 2 and disable comparators 1 and 2

w ith the internal reference voltage selected. Also stop the high-speed on-chip oscillator. Then set the BGRCR0 bit to

1 (disabled).

Set the PRC3 bit in the PRCR register to 1 (w rite enabled) before rew riting the BGRCR register.

—

(b7-b1)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

BGRCR0

Internal reference voltage (Vref)

adjustment circuit (BGR trimming

circuit) enable bit(2)

0: Enabled

1: Disabled

b3 b2 b1

b7 b6 b5 b4

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