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SH7261 Datasheet(PDF) 724 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 724 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 692 of 1312
REJ09B0320-0200
16.3.8
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive
bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset
or in deep standby mode. Each channel has independent baud rate generator control, so different
values can be set in eight channels.
0
1
2
3
4
5
6
7
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Bit:
Initial value:
R/W:
The SCBRR setting is calculated as follows:
• Asynchronous mode:
N =
× 106 − 1
64
× 22n-1 × B
P
φ
• Clocked synchronous mode:
N =
× 106 − 1
8
× 22n-1 × B
P
φ
B:
Bit rate (bits/s)
N:
SCBRR setting for baud rate generator (0
≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
P
φ:
Operating frequency for peripheral modules (MHz)
n:
Baud rate generator clock source (n
= 0, 1, 2, 3) (for the clock sources and values of n,
see table 16.3.)



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