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SH7261 Datasheet(PDF) 725 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 725 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 693 of 1312
REJ09B0320-0200
Table 16.3
SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
P
φ
0
0
1
P
φ/4
0
1
2
P
φ/16
1
0
3
P
φ/64
1
1
The bit rate error in asynchronous is given by the following formula:
Error (%) =
− 1 × 100
(N + 1)
× B × 64 × 22n-1
P
φ × 106
Table 16.4 lists examples of SCBRR settings in asynchronous mode, and table 16.5 lists examples
of SCBRR settings in clocked synchronous mode.
Table 16.4
Bit Rates and SCBRR Settings (Asynchronous Mode) (1)
P
φ (MHz)
5
6
6.144
7.3728
Bit Rate
(bit/s)
n
N
Error
(
%)
n
N
Error
(
%)
n
N
Error
(
%)
n
N
Error
(
%)
110
2
88
−0.25 2
106
−0.44 2
108
0.08
2
130
–0.07
150
2
64
0.16
2
77
0.16
2
79
0.00
2
95
0.00
300
1
129
0.16
1
155
0.16
1
159
0.00
1
191
0.00
600
1
64
0.16
1
77
0.16
1
79
0.00
1
95
0.00
1200
0
129
0.16
0
155
0.16
0
159
0.00
0
191
0.00
2400
0
64
0.16
0
77
0.16
0
79
0.00
0
95
0.00
4800
0
32
−1.36 0
38
0.16
0
39
0.00
0
47
0.00
9600
0
15
1.73
0
19
−2.34 0
19
0.00
0
23
0.00
19200
0
7
1.73
0
9
−2.34 0
9
0.00
0
11
0.00
31250
0
4
0.00
0
5
0.00
0
5
2.40
0
6
5.33
38400
0
3
1.73
0
4
−2.34 0
4
0.00
0
5
0.00



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