SH7261 datasheet(732/1348 Pages) RENESAS

732 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 700 of 1312

REJ09B0320-0200

16.3.9

FIFO Control Register (SCFCR)

SCFCR resets the quantity of data in the transmit and receive data FIFO registers, sets the trigger

data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and

written to by the CPU. It is initialized to H'0000 by a power-on reset or in deep standby mode.

R/W

RTRG[1:0]

TTRG[1:0]

—

TFRST RFRST LOOP

Bit:

Initial value:

R/W:

—————

———

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

Receive FIFO Data Trigger

Set the quantity of receive data which sets the receive

data full (RDF) flag in the serial status register (SCFSR).

The RDF flag is set to 1 when the quantity of receive

data stored in the receive FIFO register (SCFRDR) is

increased more than the set trigger number shown

below.

• Asynchronous mode • Clocked synchronous mode

00: 1

01: 4

10: 8

11: 14

00: 1

01: 2

10: 8

11: 14

7, 6

RTRG[1:0]

R/W

Note: In clock synchronous mode, to transfer the receive

data using DMAC, set the receive trigger number

to 1. If a number other than 1 is set, CPU must

read the receive data left in SCFRDR.

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