SH7261 datasheet(734/1348 Pages) RENESAS

734 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 702 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

LOOP

R/W

Loop-Back Test

Internally connects the transmit output pin (TxD) and

receive input pin (RxD) and enables loop-back testing.

0: Loop back test disabled

1: Loop back test enabled

16.3.10

FIFO Data Count Register (SCFDR)

SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data

It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of

receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is

initialized to H'0000 by a power on reset or in deep standby mode.

987654321

0000000000000000

RRRRRRRRRRRRRRRR

Bit:

Initial value:

R/W:

—

T[4:0]

—

R[4:0]

Bit

Bit Name

Initial

Value

R/W

Description

15 to 13

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

12 to 8

T[4:0]

00000

T4 to T0 bits indicate the quantity of non-transmitted

data stored in SCFTDR. H'00 means no transmit data,

and H'10 means that SCFTDR is full of transmit data.

7 to 5

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

4 to 0

R[4:0]

00000

R4 to R0 bits indicate the quantity of receive data

stored in SCFRDR. H'00 means no receive data, and

H'10 means that SCFRDR full of receive data.

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