SH7261 datasheet(737/1348 Pages) RENESAS

737 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 705 of 1312

REJ09B0320-0200

16.3.12

Line Status Register (SCLSR)

The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can

be cleared to 0 only if it has first been read (after being set to 1).

SCLSR is initialized to H'0000 by a power-on reset or in deep standby mode.

987654321

0000000000000000

RRRRRRRRRRRRRRR

R/(W)*

Bit:

Initial value:

R/W:

Note: *

Only 0 can be written to clear the flag after 1 is read.

ORER

—

Bit

Bit Name

Initial

Value

R/W

Description

15 to 1

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

ORER

R/(W)* Overrun Error

Indicates the occurrence of an overrun error.

0: Receiving is in progress or has ended normally*

[Clearing conditions]

• ORER is cleared to 0 when the chip is a power-on

reset

• ORER is cleared to 0 when 0 is written after 1 is

read from ORER.

1: An overrun error has occurred*

[Setting condition]

• ORER is set to 1 when the next serial receiving is

finished while the receive FIFO is full of 16-byte

receive data.

Notes: 1. Clearing the RE bit to 0 in SCSCR does

not affect the ORER bit, which retains its

previous value.

2. The receive FIFO data register (SCFRDR)

retains the data before an overrun error

has occurred, and the next received data

is discarded. When the ORER bit is set to

1, the SCIF cannot continue the next

serial reception.

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