SH7261 datasheet(809/1348 Pages) RENESAS

809 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 777 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

SCKD

R/W

Serial Bit Clock Direction

0: Serial bit clock is input, slave mode.

1: Serial bit clock is output, master mode.

Note: SSI0 and SSI1 permit only the following setting:

(SCKD, SWSD) = (0,0) and (1,1). Other settings

are prohibited.

SWSD

R/W

Serial WS Direction

0: Serial word select is input, slave mode.

1: Serial word select is output, master mode.

Note: SSI0 and SSI1 permit only the following setting:

(SCKD, SWSD) = (0,0) and (1,1). Other settings

are prohibited.

SCKP

R/W

Serial Bit Clock Polarity

0: SSIWS and SSIDATA change at the SSISCK falling

edge (sampled at the SCK rising edge).

1: SSIWS and SSIDATA change at the SSISCK rising

edge (sampled at the SCK falling edge).

SCKP = 0

SCKP = 1

SSIDATA input sampling timing at

the time of reception (TRMD = 0)

SSISCK rising

edge

SSISCK falling

edge

SSIDATA output change timing at

the time of transmission (TRMD = 1)

SSISCK falling

edge

SSISCK rising

edge

SSIWS input sampling timing at

the time of slave mode (SWSD = 0)

SSISCK rising

edge

SSISCK falling

edge

SSIWS output change timing at

the time of master mode (SWSD = 1)

SSISCK falling

edge

SSISCK rising

edge

SWSP

R/W

Serial WS Polarity

0: SSIWS is low for 1st channel, high for 2nd channel.

1: SSIWS is high for 1st channel, low for 2nd channel.

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