SH7261 datasheet(813/1348 Pages) RENESAS

813 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 781 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

MUEN

R/W

Mute Enable

0: Module is not muted.

1: Module is muted.



Reserved

The read value is undefined. The write value should

always be 0.

TRMD

R/W

Transmit/Receive Mode Select

0: Module is in receive mode.

1: Module is in transmit mode.

R/W

SSI Module Enable

0: Module is disabled.

1: Module is enabled.

18.3.2

Status Register (SSISR)

SSISR consists of status flags indicating the operational status of the SSI module and bits

indicating the current channel numbers and word numbers.

SSISR is initialized to H'02000003 by a power-on reset or in deep standby mode.

Bit:

Initial value:

Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is ignored.

2. The SSI clock must be kept supplied until the SSI is in the idle state.

R/W:

Bit:

Initial value:

R/W:

000000

1*2

RRRR

R/W*1 R/W*1 RRRRRRRRRR

001

1*2

RRRRRRRRRRRRRRRR

—

DMRQ UIRQ OIRQ IIRQ DIRQ

—

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CHNO[1:0] SWNO IDST

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