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SH7261 Datasheet(PDF) 817 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 817 Page - Renesas Technology Corp

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Section 18 Serial Sound Interface (SSI)
Rev. 2.00 Sep. 07, 2007 Page 785 of 1312
REJ09B0320-0200
Bit
Bit Name
Initial
Value
R/W
Description
1
SWNO
1
R
System Word Number
This status bit indicates the current word number.
• TRMD = 0 (Receive mode)
SWNO indicates which system word the data in
SSIRDR currently represents. This value will
change as the data in SSIRDR is updated from the
shift register, regardless of whether SSIRDR has
been read.
• TRMD = 1 (Transmit mode)
SWNO indicates which system word is required to
be written to SSITDR. This value will change as the
data is copied to the shift register, regardless of
whether the data is written to SSITDR.
0
IDST
1*
2
R
Idle Mode Status Flag
This status flag indicates that the serial bus activity has
stopped.
This bit is cleared if EN = 1 and the serial bus are
currently active.
This bit is automatically set to 1 under the following
conditions.
• SSI = Master transmitter (SWSD = 1 and
TRMD = 1)
This bit is set to 1 if the EN bit is cleared and the
data written to SSITDR is completely output from
the serial data input/output pin (SSIDATA), that is,
the output of the system word length is completed.
• SSI = Master receiver (SWSD = 1 and TRMD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
• SSI = Slave transmitter/receiver (SWSD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
Note: If the external master stops the serial bus clock
before the current system word is completed,
this bit is not set.
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is
ignored.
2. The SSI clock must be kept supplied until the SSI is in the idle state.



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