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SH7261 Datasheet(PDF) 818 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 818 Page - Renesas Technology Corp |
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818 / 1348 page  Section 18 Serial Sound Interface (SSI) Rev. 2.00 Sep. 07, 2007 Page 786 of 1312 REJ09B0320-0200 18.3.3 Transmit Data Register (SSITDR) SSITDR is a 32-bit register that stores data to be transmitted. Data written to this register is transferred to the shift register upon transmission request. If the data word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR. The data in the buffer can be accessed by reading this register. SSITDR is initialized to H'00000000 by a power-on reset or in deep standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 18.3.4 Receive Data Register (SSIRDR) SSIRDR is a 32-bit register that stores receive messages. Data in this register is transferred from the shift register each time data word is received. If the data word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR. SSIRDR is initialized to H'00000000 by a power-on reset or in deep standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR 0000000000000000 RRRRRRRRRRRRRRRR Bit: Initial value: R/W: Bit: Initial value: R/W: |
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