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SH7261 Datasheet(PDF) 815 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 815 Page - Renesas Technology Corp

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Section 18 Serial Sound Interface (SSI)
Rev. 2.00 Sep. 07, 2007 Page 783 of 1312
REJ09B0320-0200
Bit
Bit Name
Initial
Value
R/W
Description
26
OIRQ
0
R/W*
1
Overflow Error Interrupt Status Flag
This status flag indicates that data was supplied at a
higher rate than was required.
In either case this bit is set to 1 regardless of the value
of the OIEN bit and can be cleared by writing 0 to this
bit.
If OIRQ = 1 and OIEN = 1, an interrupt occurs.
• TRMD = 0 (Receive mode)
If OIRQ = 1, SSIRDR was not read before there
was new unread data written to it. This will lead to
the loss of a sample and a potential corruption of
multi-channel data.
Note: When an overflow error occurs, the current data
in the data buffer of this module is overwritten by
the next incoming data from the SSI interface.
• TRMD = 1 (Transmit mode)
If OIRQ = 1, SSITDR had data written to it before it
was transferred to the shift register. This will lead to
the loss of a sample and a potential corruption of
multi-channel data.
25
IIRQ
1*
2
R
Idle Mode Interrupt Status Flag
This interrupt status flag indicates whether the SSI
module is in idle state.
This bit is set regardless of the value of the IIEN bit to
allow polling.
The interrupt can be masked by clearing IIEN, but
cannot be cleared by writing to this bit.
If IIRQ = 1 and IIEN = 1, an interrupt occurs.
0: The SSI module is not in idle state.
1: The SSI module is in idle state.



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