SH7261 datasheet(812/1348 Pages) RENESAS

812 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 780 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

6 to 4

CKDV[2:0]

000

R/W

Serial Oversample Clock Divide Ratio

Sets the ratio between oversample clock*

(AUDIO_CLK, or AUDIO_X1 and AUDIO_X2) and the

serial bit clock. In addition, combining these bits and the

CKDV3 bit in the standby control register enables to

divide the clock further by 1/4. This bit is ignored if

SCKD = 0. The serial bit clock is used in the shift

• When CKDV3 = 1

000: Serial bit clock frequency = Oversample clock Frequency/1

001: Serial bit clock frequency = Oversample clock frequency/2

010: Serial bit clock frequency = Oversample clock frequency/4

011: Serial bit clock frequency = Oversample clock frequency/8

100: Serial bit clock frequency = Oversample clock frequency/16

101: Serial bit clock frequency = Oversample clock frequency/6

110: Serial bit clock frequency = Oversample clock frequency/12

111: Setting prohibited

• When CKDV3 = 0

000: Serial bit clock frequency = Oversample clock Frequency/4

001: Serial bit clock frequency = Oversample clock frequency/8

010: Serial bit clock frequency = Oversample clock frequency/16

011: Serial bit clock frequency = Oversample clock frequency/32

100: Serial bit clock frequency = Oversample clock frequency/64

101: Serial bit clock frequency = Oversample clock frequency/24

110: Serial bit clock frequency = Oversample clock frequency/48

111: Setting prohibited

Note:

* AUDIO_X1 and AUDIO_X2 is selected as

oversample clock when the PD0MD0 bit in

the port D control register (PDCR1) of PFC is

set to 0, and AUDIO_CLK is selected when

the bit is set to 1.

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