SH7261 datasheet(811/1348 Pages) RENESAS

811 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 779 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

PDTA

R/W

• DWL = 010, 011, 100, 101 (with a data word length

of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned)

The data bits used in SSIRDR or SSITDR are the

following:

Bits 31 down to (32 minus the number of bits in the

data word length specified by DWL).

That is, If DWL = 011, the data word length is 20

bits; therefore, bits 31 to 12 in either SSIRDR or

SSITDR are used. All other bits are ignored or

reserved.

• DWL = 010, 011, 100, 101 (with a data word length

of 18, 20, 22 or 24 bits), PDTA = 1 (right-aligned)

The data bits used in SSIRDR or SSITDR are the

following:

Bits (the number of bits in the data word length

specified by DWL minus 1) to 0

i.e. if DWL = 011, then DWL = 20 and bits 19 to 0

are used in either SSIRDR or SSITDR. All other bits

are ignored or reserved.

• DWL = 110 (with a data word length of 32 bits), the

PDTA setting is ignored.

All data bits in SSIRDR or SSITDR are used on the

audio serial bus.

DEL

R/W

Serial Data Delay

0: 1 clock cycle delay between SSIWS and SSIDATA

1: No delay between SSIWS and SSIDATA



Reserved

The read value is undefined. The write value should

always be 0.

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