SH7261 datasheet(810/1348 Pages) RENESAS

810 / 1348 page

Section 18 Serial Sound Interface (SSI)

Rev. 2.00 Sep. 07, 2007 Page 778 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

SPDP

R/W

Serial Padding Polarity

0: Padding bits are low.

1: Padding bits are high.

Note: When MUEN = 1, padding bits are low. (The

MUTE function is given priority.)

SDTA

R/W

Serial Data Alignment

0: Transmitting and receiving in the order of serial data

and padding bits

1: Transmitting and receiving in the order of padding

bits and serial data

PDTA

R/W

Parallel Data Alignment

This bit is ignored if CPEN = 1. When the data word

length is 32, 16 or 8 bit, this configuration field has no

meaning.

This bit applies to SSIRDR in receive mode and

SSITDR in transmit mode.

0: Parallel data (SSITDR, SSIRDR) is left-aligned

1: Parallel data (SSITDR, SSIRDR) is right-aligned.

• DWL = 000 (with a data word length of 8 bits), the

PDTA setting is ignored.

All data bits in SSIRDR or SSITDR are used on the

audio serial bus. Four data words are transmitted or

received at each 32-bit access. The first data word

is derived from bits 7 to 0, the second from bits 15

to 8, the third from bits 23 to 16 and the last data

word is derived from bits 31 to 24.

• DWL = 001 (with a data word length of 16 bits), the

PDTA setting is ignored.

All data bits in SSIRDR or SSITDR are used on the

audio serial bus. Two data words are transmitted or

received at each 32-bit access. The first data word

is derived from bits 15 to 0 and the second data

word is derived from bits 31 to 16.

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