SH7261 datasheet(867/1348 Pages) RENESAS

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 835 of 1312

REJ09B0320-0200

• Requirements of Bit Configuration Register

1-bit time (8 to 25 quanta)

SYNC_SEG

PRSEG

PHSEG1

TSEG1

4-16

2-8

TSEG2

PHSEG2

Quantum

SYNC_SEG:

Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit

edge transitions occur in this segment.)

PRSEG:

Segment for compensating for physical delay between networks.

PHSEG1:

Buffer segment for correcting phase drift (positive). (This segment is extended

when synchronisation (resynchronisation) is established.)

PHSEG2:

Buffer segment for correcting phase drift (negative). (This segment is shortened

when synchronisation (resynchronisation) is established)

TSEG1:

TSG1 + 1

TSEG2:

TSG2 + 1

The RCAN-ET Bit Rate Calculation is:

Bit Rate =

fclk

× (BRP + 1) × (TSEG1 + TSEG2 + 1)

where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1

and TSG2 register values.

CLK = Peripheral Clock

BCR Setting Constraints

TSEG1min > TSEG2

≥ SJWmax

(SJW = 1 to 4)

≤ TSEG1 + TSEG2 + 1 ≤ 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)

TSEG2

≥ 2

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