SH7261 datasheet(864/1348 Pages) RENESAS

864 / 1348 page

Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 832 of 1312

REJ09B0320-0200

19.4.3

Bit Configuration Register (BCR0, BCR1)

The bit configuration registers (BCR0 and BCR1) are 2

× 16-bit read/write register that are used to

set CAN bit timing parameters and the baud rate pre-scaler for the CAN Interface.

The Time quanta is defined as:

Timequanta =

× BRP

fclk

Where: BRP (Baud Rate Pre-scaler) is the value stored in BCR0 incremented by 1 and fclk is the

used peripheral bus frequency.

• BCR1 (Address = H'004)

Bit:

Initial value:

R/W:

0000000000000000

R/W

TSG1[3:0]

—

TSG2[2:0]

—

SJW[1:0]

—

BSP

Please refer to the table below for TSG1 and TSG2 setting.

Bits 15 to 12 — Time Segment 1 (TSG1[3:0] = BCR1[15:12]): These bits are used to set the

segment TSEG1 ( = PRSEG + PHSEG1) to compensate for edges on the CAN Bus with a positive

phase error. A value from 4 to 16 time quanta can be set.

Bit 15:

TSG1[3]

Bit 14:

TSG1[2]

Bit 13:

TSG1[1]

Bit 12:

TSG1[0] Description

Setting prohibited (Initial value)

Setting prohibited

PRSEG + PHSEG1 = 4 time quanta

PRSEG + PHSEG1 = 5 time quanta

PRSEG + PHSEG1 = 16 time quanta

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