SH7261 datasheet(865/1348 Pages) RENESAS

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Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 833 of 1312

REJ09B0320-0200

Bit 11: Reserved. The written value should always be '0' and the returned value is '0'.

Bits 10 to 8 — Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the

segment TSEG2 ( = PHSEG2) to compensate for edges on the CAN Bus with a negative phase

error. A value from 2 to 8 time quanta can be set as shown below.

Bit 10:

TSG2[2]

Bit 9:

TSG2[1]

Bit 8:

TSG2[0] Description

Setting prohibited (Initial value)

PHSEG2 = 2 time quanta (conditionally prohibited) See the table

below for TSG1 and TSG2 setting.

PHSEG2 = 3 time quanta

PHSEG2 = 4 time quanta

PHSEG2 = 5 time quanta

PHSEG2 = 6 time quanta

PHSEG2 = 7 time quanta

PHSEG2 = 8 time quanta

Bits 7 and 6: Reserved. The written value should always be '0' and the returned value is '0'.

Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the

synchronisation jump width.

Bit 5:

SJW[1]

Bit 4:

SJW[0]

Description

Synchronisation Jump width = 1 time quantum (Initial value)

Synchronisation Jump width = 2 time quanta

Synchronisation Jump width = 3 time quanta

Synchronisation Jump width = 4 time quanta

Bits 3 to 1: Reserved. The written value should always be '0' and the returned value is '0'.

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