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SH7261 Datasheet(PDF) 917 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 917 Page - Renesas Technology Corp

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Section 20 IEBus
TM Controller (IEB) [R5S72612] [R5S72613]
Rev. 2.00 Sep. 07, 2007 Page 885 of 1312
REJ09B0320-0200
(a)
Master Transmission
The master unit transmits the data bits and parity bit to the slave unit to write data from the master
unit to the slave unit. The slave unit receives the data bits and parity bit, and returns an
acknowledgement if the parity bit is even and the receive buffer is empty. If the parity bit is odd or
the receive buffer is not empty, the slave unit does not accept the corresponding data and does not
return an acknowledgement.
When the slave unit does not return an acknowledgement, the master unit retransmits the data.
This operation is repeated until either an acknowledgement from the slave unit is detected or the
maximum number of data transfer bytes is reached.
When the parity is even and the acknowledgement is output from the slave unit, the master unit
transmits the subsequent data if data remains and the maximum number of transfer bytes are not
exceeded.
In the case of broadcast communications, the slave unit does not return the acknowledgement, and
the master unit transfers data byte by byte.
(b)
Master Reception
The master unit outputs synchronous signals corresponding to all data bits to be read from the
slave unit.
The slave unit outputs the data bits and parity bit on the bus in accordance with the synchronous
signals from the master unit.
The master unit reads the parity bit output from the slave unit, and checks the parity. If the parity
is not even, or the receive buffer is not empty, the master unit rejects acceptance of the data, and
does not return the acknowledgement. The master unit reads the same data repeatedly if the
number of data does not exceed the maximum number of transfer bytes in one frame. If the parity
is even and the receive buffer is empty, the master unit accepts data and returns an
acknowledgement. The master unit reads in the subsequent data if the number of data does not
exceed the maximum number of transfer bytes in one frame.



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