SH7261 datasheet(938/1348 Pages) RENESAS

938 / 1348 page

Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 906 of 1312

REJ09B0320-0200

20.3.10

IEBus Reception Master Address Register 2 (IEMA2)

IEMA2 indicates the upper eight bits of the communications destination master unit address in

slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the

contents are changed at the time of setting the RXS flag in IERSR.

If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer

is not in the receive enabled state at control field reception, a receive error interrupt is generated

and the upper eight bits of the master address are stored in IEMA2. This register cannot be

modified by a write.

IEMA2 is initialized by a power-on reset or in deep standby.

76543210

Bit:

Initial value:

R/W:

00000000

RRRRRRRR

IMAU8

Bit

Bit Name

Initial

Value

R/W

Description

7 to 0

IMAU8

All 0

Upper Eight Bits of IEBus Reception Master Address

Indicates the upper eight bits of the communications

destination master unit address in slave/broadcast

reception. This register is enabled when

slave/broadcast reception starts, and the contents are

changed at the time of setting the RXS flag. If a

broadcast receive error interrupt is selected by the DEE

bit in IECTR and the receive buffer is not in the receive

enabled state at control field reception, a receive error

interrupt is generated and the upper eight bits of the

master address are stored in IEMA2.

SH7261 Datasheet(PDF) 938 Page - Renesas Technology Corp