SH7261 datasheet(951/1348 Pages) RENESAS

951 / 1348 page

Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 919 of 1312

REJ09B0320-0200

20.3.18

IEBus Receive Status Register (IERSR)

IERSR detects receive busy, receive start, receive normal completion, or receive completion with

an error. Each status flag in IERSR corresponds to a bit in the IEIER that enables/disables each

interrupt. This register is cleared by writing 1 to each bit.

IERSR is initialized by a power-on reset or in deep standby.

76543210

Bit:

Initial value:

R/W:

00000000

R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

BSY

RXS

RXF

EDE

EOVE

RXE

RTME

EDLE

EPE

Bit

Bit Name

Initial

Value

R/W

Description

RXBSY

R/(W)*

Receive Busy

Indicates that the receive data is stored in the receive

data buffer (IERB001 to IERB128). Clear this bit after

reading out all data. The next receive data cannot be

received while this bit is set.

[Setting condition]

• When all receive data has been written to the

receive data buffer.

[Clearing condition]

• When 1 is written

RXS

R/(W)*

Receive Start Detection

Indicates that the IEB starts reception.

[Setting condition]

• When the data from the master unit to message

length field has been received correctly in slave

reception

[Clearing condition]

• When 1 is written

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