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SH7261 Datasheet(PDF) 975 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 975 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 943 of 1312
REJ09B0320-0200
Section 21 CD-ROM Decoder (ROM-DEC)
The CD-ROM decoder (ROM-DEC) decodes streams of data transferred from the CD-DSP. When
the medium is CD-DA*
1, the data stream is not input to the CD-ROM decoder because it consists
of PCM data. In the case of CD-ROM*
2, the stream of data is input and the CD-ROM decoder
performs sync code detection and maintenance, descrambling, ECC correction, and EDC
checking, and outputs the resulting stream of data.
However, since the stream received by the CD-ROM decoder is assumed to consist of data from a
CD-ROM transferred via the SSI, the decoder does not bother with the subcodes defined in the
CD-DA standard.
Notes: 1. Compliant with JIS S 8605 (Red Book)
2. Compliant with JIS X 6281 (Yellow Book)
21.1
Features
• Sync-code detection and maintenance
Detects sync codes from the CD-ROM and is capable of providing sync-code maintenance
(automatic interpolation of sync codes) when the sync code cannot be detected because of
defects such as scratches on the disc.
Supported maintenance modes are automatic sync maintenance mode, external sync mode,
interpolated sync mode, and interpolated sync plus external sync mode.
• Descrambling
• ECC support
P-parity-based correction, Q-parity-based correction, PQ correction, and QP correction are
available.
PQ correction and QP correction can be applied repeatedly up to three times. This, however,
depends on the speed of the CD. For example, three iterations are possible when the CD-ROM
decoder is operating at 60 MHz with a double-speed CD drive.
Two buffers are provided due to the need for ECC correction. This allows parallel operation,
where ECC correction is performed in one buffer while the data stream is being received in the
other.
• EDC checking
The EDC is checked before and after correction based on the ECC. Furthermore, an operating
mode is available in which, if the result of pre-correction EDC checking indicates no errors,
ECC correction is not performed regardless of the result of syndrome calculation.



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