SH7261 datasheet(977/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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977 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 945 of 1312

REJ09B0320-0200

21.2

Block Diagrams

Figure 21.2 is a block diagram of the CD-ROM decoder functions of this LSI and the bus bridge

for connection to the peripheral bus, that is, of the elements required to implement the CD-ROM

decoder function.

Bus bridge (peripheral bus

⇔ ROM-DEC bus)

INTC interrupt and DMAC activation control

INTC DMAC

Stream data

Descrambler

EDC

Sync code

detection/

maintenance

Mode

determination

Syndrome

calculator

Core of CD-ROM decoder

Memory

(2 buffers for ECC)

Memory

control

ECC control

Timing

generation

SH-2A CPU

Peripheral bus controller

Figure 21.2 ROM-DEC Block Diagram

The core of the CD-ROM decoder executes a series of processing required for CD-ROM

decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based

correction), and EDC checking. The core includes sufficient memory to hold two sectors.

SH7261 Datasheet(PDF) 977 Page - Renesas Technology Corp