SH7261 datasheet(980/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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980 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 948 of 1312

REJ09B0320-0200

Figure 21.5 is a schematic diagram of the stream-data output control block.

On recognizing that one sector of CD-ROM data is ready in the core of the CD-ROM decoder, this

block ensures that the output stream-data register in the bus bridge section is empty and then starts

to acquire the data for output from the core of the CD-ROM decoder

Output

stream data

Input stream-data

control signal

Output stream-data

protocol controller

Figure 21.5 Schematic Diagram of the Stream-Data Output Control Block

This block has functions related to INTC interrupts and DMAC activation control such as

suspending and masking of interrupts, turning interrupt flags off after they are read, asserting the

activation signal to the DMAC, and negating the activation signal according to the detected

amount of data that has been transferred.

SH7261 Datasheet(PDF) 980 Page - Renesas Technology Corp