SH7261 datasheet(981/1348 Pages) RENESAS

981 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 949 of 1312

REJ09B0320-0200

21.3

The ROM-DEC has the following registers.

Table 21.1

Name

Abbreviation

R/W

Initial

Value

Address

Access

Size

ROM-DEC enable control register

CROMEN

R/W

H'00

H'E8000000

Sync code-based synchronization control

CROMSY0

R/W

H'89

H'E8000001

Decoding mode control register

CROMCTL0

R/W

H'82

H'E8000002

EDC/ECC check control register

CROMCTL1

R/W

H'D1

H'E8000003

Automatic decoding stop control register

CROMCTL3

R/W

H'00

H'E8000005

Decoding option setting control register

CROMCTL4

R/W

H'00

H'E8000006

HEAD20 to HEAD22 representation control

CROMCTL5

R/W

H'00

H'E8000007

Sync code status register

CROMST0

H'00

H'E8000008

Post-ECC header error status register

CROMST1

H'00

H'E8000009

Post-ECC subheader error status register

CROMST3

H'00

H'E800000B

Header/subheader validity check status

CROMST4

H'00

H'E800000C

Mode determination and link sector

detection status register

CROMST5

H'00

H'E800000D

ECC/EDC error status register

CROMST6

H'00

H'E800000E

Buffer status register

CBUFST0

H'00

H'E8000014

Decoding stoppage source status register

CBUFST1

H'00

H'E8000015

Buffer overflow status register

CBUFST2

H'00

H'E8000016

Pre-ECC correction header:

minutes data register

HEAD00

H'00

H'E8000018

Pre-ECC correction header:

seconds data register

HEAD01

H'00

H'E8000019

Pre-ECC correction header:

frames (1/75 second) data register

HEAD02

H'00

H'E800001A

Pre-ECC correction header:

mode data register

HEAD03

H'00

H'E800001B

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