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SH7261 Datasheet(PDF) 986 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 986 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 954 of 1312
REJ09B0320-0200
Table 21.2
Register Settings for Sync Code Maintenance Modes
SY_AUT
SY_IEN
SY_DEN
Operating Mode
1
Automatic sync maintenance mode
0
0
1
External sync mode
0
1
0
Interpolated sync mode
0
1
1
Interpolated sync plus external sync mode
0
0
0
Setting prohibited
21.3.3
Decoding Mode Control Register (CROMCTL0)
CROMCTL0 enables/disables the various functions, selects criteria for mode or form
determination, and specifies the sector type. The setting of this register becomes valid at the
sector-to-sector transition
76543210
Bit:
Initial value:
R/W:
10000010
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MD_
DESC
—
MD_
AUTO
MD_
AUTOS1
MD_
AUTOS2
MD_SEC[2:0]
Bit
Bit Name
Initial
Value
R/W
Description
7
MD_DESC
1
R/W
Descrambling Function ON/OFF
0: Descrambling function is off
1: Descrambling function is on
6
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
5
MD_AUTO
0
R/W
Automatic Mode/Form Detection ON/OFF
0: Off
1: On
Detectable formats are Mode 0, Mode 1, Mode 2 (non-
XA), Mode 2 Form 1, and Mode 2 Form 2. If the mode
and form cannot be detected, the sector is taken to be
in the same mode and form as the previous sector. If
the mode and form of the first sector after decoding
starts is undetectable, the setting of the MD_SEC[2:0]
bits is used as the initial value.



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