SH7261 datasheet(990/1348 Pages) RENESAS

990 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 958 of 1312

REJ09B0320-0200

21.3.6

Decoding Option Setting Control Register (CROMCTL4)

CROMCTL4 enables/disables buffering control at link block detection, specifies the information

indicated by the status register, and controls the ECC correction mode. The setting of this register

becomes valid at the sector-to-sector transition

76543210

Bit:

Initial value:

R/W:

00000000

R/W

LINK

OFF

LINK2

—

ER0

SEL

NO_

ECC

———

Bit

Bit Name

Initial

Value

R/W

Description

LINKOFF

R/W

Buffering Control at Link Block Detection

0: On

1: Off

When this bit is set to 1, buffering control is not

performed when a link block is detected. The link block

is processed as normal sectors.

However, link-block detection processing does proceed,

and the results are reflected in the values of bits 3 to 0

in the CROMST5 register.

LINK2

R/W

Link Block Detection Condition

0: The block is regarded as a link block when either

run-out 1 or 2 and both run-in 3 and 4 have been

detected.

1: The block is regarded as a link block when two out

of run-out 1 and 2 and "link" have been detected.

When this bit is set to 1, buffering control for link blocks

is disabled (link blocks are processed as normal

sectors). The condition for setting of the LINK_ON bit in

CROMST5 is decoding of the link sector.



R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

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