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SH7261 Datasheet(PDF) 993 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 993 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 961 of 1312
REJ09B0320-0200
Bit
Bit Name
Initial
Value
R/W
Description
1
ST_SECS
0
R
Indicates that a sector has been processed as a short
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from the sector prior to the currently
being decoded sector.
0
ST_SECL
0
R
Indicates that a sector has been processed as a long
sector with the aid of interpolated sync codes. If this bit
is set to 1, stop decoding immediately and retry the
procedure starting from two sectors prior to the sector
currently being decoded.
21.3.9
Post-ECC Header Error Status Register (CROMST1)
CROMST1 indicates error status in the post-ECC header.
76543210
Bit:
Initial value:
R/W:
00000000
RRRRRRRR
——
—
—
ER2_
HEAD0
ER2_
HEAD1
ER2_
HEAD2
ER2_
HEAD3
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
3
ER2_HEAD0
0
R
Indicates an error status in the minutes field of the
header after ECC correction.
2
ER2_HEAD1
0
R
Indicates an error status in the seconds field of the
header after ECC correction.
1
ER2_HEAD2
0
R
Indicates an error status in the frames (1/75 second)
field of the header after ECC correction.
0
ER2_HEAD3
0
R
Indicates an error status in the mode field of the header
after ECC correction.



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