SH7261 datasheet(989/1348 Pages) RENESAS

989 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 957 of 1312

REJ09B0320-0200

21.3.5

Automatic Decoding Stop Control Register (CROMCTL3)

CROMCTL3 is used to select abnormal conditions on which decoding will be automatically

stopped. When decoding is stopped in response to any of the selected conditions, an IBUF

interrupt is generated and the condition is indicated in the CBUFST1 register. The setting of this

76543210

Bit:

Initial value:

R/W:

00000000

R/W

STP_

ECC

STP_

EDC

—

STP_

MIN

———

Bit

Bit Name

Initial

Value

R/W

Description

STP_ECC

R/W

When this bit is set to 1, decoding is stopped if an error

is found to be not correctable by ECC correction.

STP_EDC

R/W

When this bit is set to 1, decoding is stopped if post-

correction EDC checking indicates an error.



R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

STP_MD

R/W

When this bit is set to 1, decoding is stopped if the

sector has a mode or form setting that does not match

those of the immediately preceding sector.

STP_MIN

R/W

When this bit is set to 1, decoding is stopped if a non-

sequential minutes, seconds, or frames (1/75 second)

value is encountered.

2 to 0



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

Note:

The setting of this register is reapplied on each sector-to-sector transition.

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