SH7261 datasheet(991/1348 Pages) RENESAS

991 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 959 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

ER0SEL

R/W

CD-ROM Data-Related Status Register Setting

Condition

0: Information is on the sector being decoded.

1: Information is on the latest sector that has been

buffered.

This condition affects the information given by bits 5 to

0 in the CROMST0 register, bits 7 to 1 in the

CROMST4 and CROMST5 registers, and HEAD00 to

HEAD02.

NO_ECC

R/W

ECC correction mode when the result of the EDC check

before ECC correction was 'pass'

When this bit is set to 1, ECC correction is not

performed if the result of pre-correction EDC checking

is a 'pass', regardless of the results of syndrome

calculation.

2 to 0



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

Note:

The setting of this register is reapplied on each sector-to-sector transition.

21.3.7

HEAD20 to HEAD22 Representation Control Register (CROMCTL5)

CROMCTL5 specifies the representation mode for HEAD20 to HEAD22.

76543210

Bit:

Initial value:

R/W:

00000000

R/W

—

————

—

MSF_

LBA_SEL

Bit

Bit Name

Initial

Value

R/W

Description

7 to 1



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

MSF_LBA_

SEL

R/W

HEAD20 to HEAD22 Representation Mode

0: BCD M, F, and S values in the header as is

1: Total sector number in HEX

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