SH7672 datasheet(381/1292 Pages) RENESAS

381 / 1292 page

Section 9 Clock Pulse Generator (CPG)

Rev. 1.00 Nov. 14, 2007 Page 355 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

13, 12

CKOEN[1:0] 00

R/W

Clock Output Enable

Specifies the CKIO pin outputs clock signals, or is set

to a fixed level or high impedance (Hi-Z) during

normal operation mode, standby mode, or

cancellation of standby mode.

If these bits are set to 01, the CKIO pin is fixed at low

during standby mode or cancellation of standby

mode. Therefore, the malfunction of an external circuit

caused by an unstable CKIO clock during cancellation

of standby mode can be prevented. In clock operating

mode 2, the CKIO pin functions as an input

regardless of the value of these bits.

In normal operation

In standby mode

Output

Output off (Hi-Z)

Output

Low-level output

Output

(unstable clock output)

Output off (Hi-Z)

11, 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

9, 8

STC[1:0]

R/W

Frequency Multiplication Ratio of PLL Circuit

00:

× 8 time

01:

× 12 times

10: Reserved (setting prohibited)

11: Reserved (setting prohibited)

7 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7672 Datasheet(PDF) 381 Page - Renesas Technology Corp

SH7672 Datasheet(HTML) 381 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL