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SH7672 Datasheet(PDF) 442 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 442 Page - Renesas Technology Corp |
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442 / 1292 page ![]() Section 12 Ethernet Controller (EtherC) Rev. 1.00 Nov. 14, 2007 Page 416 of 1262 REJ09B0437-0100 12.3.14 Frame Receive Error Counter Register (FRECR) FRECR is a 32-bit counter that indicates the number of frames input from the PHY for which a receive error was indicated by the RX-ER pin. FRECR is incremented each time the RX-ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FREC[31:16] FREC[15:0] Bit Bit Name Initial Value R/W Description 31 to 0 FREC[31:0] All 0 R/W Frame Receive Error Count These bits indicate the count of errors during frame reception. |
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