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SH7672 Datasheet(PDF) 438 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 438 Page - Renesas Technology Corp |
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438 / 1292 page  Section 12 Ethernet Controller (EtherC) Rev. 1.00 Nov. 14, 2007 Page 412 of 1262 REJ09B0437-0100 12.3.10 Delayed Collision Detect Counter Register (CDCR) CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter value is cleared to 0 by a write to this register with any value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W COSDC[31:16] COSDC[15:0] Bit Bit Name Initial Value R/W Description 31 to 0 COSDC[31:0] All 0 R/W Delayed Collision Detect Count These bits indicate the number of delayed collisions on all lines from a start of transmission. |
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