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SH7672 Datasheet(PDF) 437 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 437 Page - Renesas Technology Corp |
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437 / 1292 page ![]() Section 12 Ethernet Controller (EtherC) Rev. 1.00 Nov. 14, 2007 Page 411 of 1262 REJ09B0437-0100 12.3.9 Transmit Retry Over Counter Register (TROCR) TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed, TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TROC[31:16] TROC[15:0] Bit: Initial value: R/W: Bit: Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 0 TROC[31:0] All 0 R/W Transmit Retry Over Count These bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. |
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