SH7672 datasheet(481/1292 Pages) RENESAS

481 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 455 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

value

R/W

Description

PRECE

R/W

PRE Bit Copy Directive

0: Indicates the PRF bit state in bit RFS1 of the receive

descriptor

1: Occurrence of the corresponding interrupt is not

indicated in bit RFS1 of the receive descriptor

CERFCE

R/W

CERF Bit Copy Directive

0: Indicates the CERF bit state in bit RFS0 of the

receive descriptor

1: Occurrence of the corresponding interrupt is not

indicated in bit RFS0 of the receive descriptor

13.2.9

Receive Missed-Frame Counter Register (RMFCR)

RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not

transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive

frames in the FIFO are discarded. The number of frames discarded at this time is counted. When

the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the

counter value is cleared to 0. Write operations to this register have no effect.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRR



MFC[15:0]

Bit

Bit Name

Initial

value

R/W

Description

31 to 16



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

15 to 0

MFC[15:0]

All 0

Missed-Frame Counter

Indicate the number of frames that are discarded and

not transferred to the receive buffer during reception.

SH7672 Datasheet(PDF) 481 Page - Renesas Technology Corp

SH7672 Datasheet(HTML) 481 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL