SH7672 datasheet(484/1292 Pages) RENESAS

484 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 458 of 1262

REJ09B0437-0100

13.2.12

Receiving Method Control Register (RMCR)

RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in

EDRRR when a frame is received. This register must be set during the receiving-halt state.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRR

R/W







RNC

Bit

Bit Name

Initial

value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

RNC

R/W

Receive Enable Control

0: When reception of one frame is completed, the E-

DMAC writes the receive status into the descriptor

and clears the RR bit in EDRRR

1: When reception of one frame is completed, the E-

DMAC writes the receive status into the descriptor,

reads the next descriptor, and prepares to receive

the next frame

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