SH7672 datasheet(482/1292 Pages) RENESAS

482 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 456 of 1262

REJ09B0437-0100

13.2.10

Transmit FIFO Threshold Register (TFTR)

TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the

first transmission is started. The actual threshold is 4 times the set value. The EtherC starts

transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified

by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting

this register, do so in the transmission-halt state.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

R/W









TFT[10:0]

Bit

Bit Name Initial value R/W

Description

31 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

10 to 0

TFT[10:0] All 0

R/W

Transmit FIFO threshold

When setting a transmit FIFO, the FIFO must be set to

a smaller value than the specified value of the FIFO

capacity by FDR.

H'00: Store and forward modes

H'01 to H'0C: Setting prohibited

H'0D: 52 bytes

H'0E: 56 bytes

H'1F: 124 bytes

H'20: 128 bytes

H'3F: 252 bytes

H'40: 256 bytes

H'7F: 508 bytes

H'80: 512 bytes

H'81 to H'200: Setting prohibited

Note:

When starting transmission before one frame of data write has completed, take care the

generation of the underflow.

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