SH7672 datasheet(488/1292 Pages) RENESAS

488 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 462 of 1262

REJ09B0437-0100

13.2.17

Transmission-Descriptor Fetch Address Register (TDFAR)

TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor

information from the transmission descriptor. Which transmission descriptor information is used

for processing by the E-DMAC can be recognized by monitoring addresses displayed in this

from the value read from this register.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

TDFA[31:16]

RRRRRRRRRRRRRRRR

TDFA[15:0]

Bit

Bit Name

Initial

value

R/W

Description

31 to 0

TDFA[31:0]

All 0

Transmission-Descriptor Fetch Address

These bits can only be read. Writing is prohibited.

13.2.18

Flow Control FIFO Threshold Register (FCFTR)

FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the

threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the

receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The

condition to start the flow control is decided by taking OR operation on the two thresholds.

Therefore, the flow control by the two thresholds is independently started.

When flow control is performed according to the RFD bits setting, if the setting is the same as the

depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when

the remaining FIFO is (FIFO data

− 64) bytes. For instance, when RFD in FDR = 1 and RFD in

FCFTR

= 1, flow control is started when (512 − 64) bytes of data is stored in the receive FIFO.

The value set in the RFD bits in this register should be equal to or less than those in FDR.

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