SH7672 datasheet(489/1292 Pages) RENESAS

489 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 463 of 1262

REJ09B0437-0100

0000000000000111

RRRRRRRRRRRRR

R/W

0000000000000000

RRRRRRRRRRRRR

R/W



RFF[2:0]



RFD[2:0]

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

Bit

Bit Name

Initial

value

R/W

Description

31 to 19



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

18 to 16

RFF[2:0]

111

R/W

Receive Frame Number Flow Control Threshold

000: When one receive frame has been stored in the

receive FIFO

001: When two receive frames have been stored in the

receive FIFO

110: When seven receive frames have been stored in

the receive FIFO

111: When eight receive frames have been stored in

the receive FIFO

15 to 3



All 0



Reserved

These bits are always read as 0. The write value

should always be 0.

2 to 0

RFD[2:0]

000

R/W

Receive Byte Flow Control Threshold

000: When (256

− 64) bytes of data is stored in the

receive FIFO

001: When (512

− 64) bytes of data is stored in the

receive FIFO

Other than above: Setting prohibited

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