SH7672 datasheet(491/1292 Pages) RENESAS

491 / 1292 page

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 1.00 Nov. 14, 2007 Page 465 of 1262

REJ09B0437-0100

13.2.20

Transmit Interrupt Register (TRIMD)

TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back

completion for each frame using the TWB bit in EESR and an interrupt on transmit operations.

Bit:

Initial Value:

R/W:

Bit:

Initial Value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRR

RRRRRRRRR

R/W







TIS

Bit

Bit Name

Initial

value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TIS

R/W

Transmit Interrupt Setting

0: Write-back completion for each frame is not notified

1: Write-backed completion for each frame using the

TWB bit in EESR is notified

13.2.21

Checksum Mode Register (CSMR)

CSMR is a 32-bit readable/writable register that specifies the checksum operating mode. Set this

Bit:

Initial Value:

R/W:

1100000000000000

R/W

RRRRRRRRRRRRRR

0000000000011010

RRRRRRRRRR

R/W

CSEBL CSMD





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