SH7672 datasheet(158/1292 Pages) RENESAS

158 / 1292 page

Section 6 Interrupt Controller (INTC)

Rev. 1.00 Nov. 14, 2007 Page 132 of 1262

REJ09B0437-0100

Figure 6.1 shows a block diagram of the INTC.

UBC

H-UDI

DMAC

CMT

BSC

WDT

MTU2

MTU2S

POE2

ADC

IIC3

SCIF

UBC:

H-UDI:

DMAC:

CMT:

BSC:

WDT:

EtherC:

A-DMAC:

HIF:

USB:

STIF:

SSI:

SDHI:

IIC3:

SCIF:

ICR0:

ICR1:

ICR2:

IRQRR:

PINTER:

PIRR:

IBCR:

IBNR:

IPR01, IPR02, IPR05 to IPR14:

CPU

Module bus

I3 I2 I1 I0

PINTER

IBCR

IPR01, IPR02,

IPR05 to IPR14

ICR0

ICR2

PIRR

IBNR

ICR1

IRQRR

PINT7 to PINT0

IRQ7 to IRQ0

NMI

IRQOUT

IPR

Input control

INTC

(Interrupt request)

Priority

identifier

Com-

parator

Interrupt

request

Bus

interface

User break controller

High-performance user debugging interface

Direct memory access controller

Compare match timer

Bus state controller

Watchdog timer

Ethernet controller

DMAC with encryption/decryption

and forward error correction core

Host interface

USB2.0 host/function module

Stream interface

Serial sound interface

SD host interface

I2C bus interface 3

Serial communication interface with FIFO

Interrupt control register 0

Interrupt control register 1

Interrupt control register 2

IRQ interrupt request register

PINT interrupt enable register

PINT interrupt request register

Bank control register

Bank number register

Interrupt priority registers 01, 02,

05 to 14

[Legend]

Figure 6.1 Block Diagram of INTC

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