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SH7672 Datasheet(PDF) 154 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 154 Page - Renesas Technology Corp |
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154 / 1292 page  Section 5 Exception Handling Rev. 1.00 Nov. 14, 2007 Page 128 of 1262 REJ09B0437-0100 5.8 Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 5.12. Table 5.12 Stack Status After Exception Handling Ends Exception Type Stack Status Address error 32 bits 32 bits SR Address of instruction after executed instruction SP Interrupt 32 bits 32 bits SR Address of instruction after executed instruction SP Register bank error (overflow) 32 bits 32 bits SR Address of instruction after executed instruction SP Register bank error (underflow) 32 bits 32 bits SR Start address of relevant RESBANK instruction SP Trap instruction 32 bits 32 bits SR Address of instruction after TRAPA instruction SP Slot illegal instruction 32 bits 32 bits SR Jump destination address of delayed branch instruction SP |
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