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SH7672 Datasheet(PDF) 153 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 153 Page - Renesas Technology Corp |
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153 / 1292 page  Section 5 Exception Handling Rev. 1.00 Nov. 14, 2007 Page 127 of 1262 REJ09B0437-0100 5.7 When Exception Sources Are Not Accepted When an address error, FPU exception, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.11. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Address Error FPU exception Register Bank Error (Overflow) Interrupt Immediately after a delayed branch instruction* Not accepted Not accepted Not accepted Not accepted Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF |
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