SH7672 datasheet(150/1292 Pages) RENESAS

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Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 124 of 1262

REJ09B0437-0100

5.6.2

Trap Instructions

When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU

operates as follows:

1. The exception service routine start address which corresponds to the vector number specified

in the TRAPA instruction is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

4. After jumping to the exception service routine start address fetched from the exception

handling vector table, program execution starts. The jump that occurs is not a delayed branch.

5.6.3

Slot Illegal Instructions

An instruction placed immediately after a delayed branch instruction is said to be placed in a delay

slot. When the instruction placed in the delay slot is an undefined code (including an FPU

instruction or FPU-related CPU instruction in FPU module standby mode), an instruction that

rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU

instruction, slot illegal exception handling starts if such kind of instruction is decoded. When the

FPU is in the module standby state, the floating-point operation instruction and FPU-related CPU

instruction are handled as an undefined code; when such an instruction is placed in the delay slot,

slot illegal exception handling starts if the instruction is decoded. The CPU operates as follows:

1. The exception service routine start address is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the

delayed branch instruction immediately before the undefined code, the instruction that rewrites

the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU

instruction.

4. After jumping to the exception service routine start address fetched from the exception

handling vector table, program execution starts. The jump that occurs is not a delayed branch.

5.6.4

General Illegal Instructions

When an undefined code (including an FPU instruction or FPU-related CPU instruction in FPU

module standby mode) placed anywhere other than immediately after a delayed branch instruction

(i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. When the

FPU is in the module standby state, the floating-point operation instruction and FPU-related CPU

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