SH7672 datasheet(149/1292 Pages) RENESAS

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Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 123 of 1262

REJ09B0437-0100

5.6

Exceptions Triggered by Instructions

5.6.1

Types of Exceptions Triggered by Instructions

Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal

instructions, and integer division exceptions, as shown in table 5.10.

Table 5.10

Types of Exceptions Triggered by Instructions

Type

Source Instruction

Comment

Trap instruction

TRAPA

Slot illegal

instructions

Undefined code placed

immediately after a delayed

branch instruction (delay slot)

(including the FPU instruction and

FPU-related CPU instruction in

FPU module standby mode),

instructions that rewrite the PC,

32-bit instructions, RESBANK

instruction, DIVS instruction, and

DIVU instruction

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that rewrite the PC: JMP, JSR,

BRA, BSR, RTS, RTE, BT, BF, TRAPA,

BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N

32-bit instructions: BAND.B, BANDNOT.B,

BCLR.B, BLD.B, BLDNOT.B, BOR.B,

BORNOT.B, BSET.B, BST.B, BXOR.B,

MOV.B@disp12, MOV.W@disp12,

MOV.L@disp12, MOVI20, MOVI20S,

MOVU.B, MOVU.W.

General illegal

instructions

Undefined code anywhere

besides in a delay slot (including

the FPU instruction and FPU-

related CPU instruction in FPU

module standby mode)

Division by zero

DIVU, DIVS

Integer division

exceptions

Negative maximum value

÷ (−1)

DIVS

Floating-point

operation

instruction

Instructions that will cause Invalid

Operation Exception or Divide by

Zero Exception defined in the

IEEE754 standard, and

instructions that may cause

Overflow Exception, Underflow

Exception, or Incorrectness

Exception

FADD, FSUB, FMUL, FDIV, FMAC,

FCMP/EQ, FCMP/GT, FLOAT,

FTRC,FCNVDS, FCNVSD, FSQRT

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