SH7672 datasheet(152/1292 Pages) RENESAS

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Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 126 of 1262

REJ09B0437-0100

5.6.6

Floating-Point Operation Instruction

In the floating-point status/control register (FPSCR), FPU exception occurs if the V, Z, O, U, or I

bit in the FPU exception enable field (Enable) is set. This indicates that a floating-point operation

instruction has caused any of the exceptions defined in the IEEE754 standard: invalid operation

exception, overflow exception (likely instruction), underflow exception (likely instruction), or

incorrectness exception (likely instruction).

The following floating-point operation instructions may become exception sources:

FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS,

FCNVSD, FSQRT

An FPU exception occurs only when the corresponding enable bit is set. When the FPU detects an

exception source, the FPU discontinues its operation and notifies the CPU of the occurrence of an

exception. When exception handling is started, the CPU operates as follows:

1. The start address of the exception service routine corresponding to the FPU exception that has

occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved in the stack.

3. The program counter (PC) is saved in the stack. The start address of the instruction following

the instruction executed last is the value to be saved in the PC.

4. To start executing the program, a jump occurs to the start address of the exception service

routine fetched from the exception handling vector table. This jump is not a delayed branch.

The FPU exception flag filed (Flag) in the FPSCR is always updated irrespective of whether it is

capable of accepting FPU exceptions and remains set until it is cleared explicitly by an instruction

from the user. The FPU exception source field (Cause) in the FPSCR changes each time an FPU

instruction is executed.

When the FPU exception enable field (Enable) in the FPSCR is set and when the QIS bit in the

FPSCR is set, FPU exception starts if qNaN or

±∞ is entered into the source of the floating-point

operation instruction.

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