SH7672 datasheet(146/1292 Pages) RENESAS

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Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 120 of 1262

REJ09B0437-0100

5.5

Interrupts

5.5.1

Interrupt Sources

Table 5.8 shows the sources that start up interrupt exception handling. These are divided into

NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules.

Table 5.8

Interrupt Sources

Type

Request Source

Number of

Sources

NMI

NMI pin (external input)

User break

User break controller (UBC)

H-UDI

High-performance user debugging interface (H-UDI)

IRQ

IRQ0 to IRQ7 pins (external input)

Direct memory access controller (DMAC)

Ethernet controller (EtherC)

Compare match timer (CMT)

Bus state controller (BSC)

Watchdog timer (WDT)

Encryption/decryption and forward error correction

core conjunction DMAC (A-DMAC)

Stream interface (STIF)

Host interface (HIF)

Serial sound interface_0 (SSI_0)

Serial sound interface_1 (SSI_1)

SD host interface (SDHI)

USB2.0 host/function module (USB)

2C bus interface 3 (IIC3)

On-chip peripheral module

Serial communication interface with FIFO (SCIF)

Each interrupt source is allocated a different vector number and vector table offset. See table 6.4 in

section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table

address offsets.

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