SH7672 datasheet(144/1292 Pages) RENESAS

144 / 1292 page

Section 5 Exception Handling

Rev. 1.00 Nov. 14, 2007 Page 118 of 1262

REJ09B0437-0100

5.3.2

Address Error Exception Handling

When an address error occurs, the bus cycle in which the address error occurred ends.* When the

executing instruction then finishes, address error exception handling starts. The CPU operates as

follows:

1. The exception service routine start address which corresponds to the address error that

occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved on the stack.

3. The program counter (PC) is saved on the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

4. After jumping to the exception service routine start address fetched from the exception

handling vector table, program execution starts. The jump that occurs is not a delayed branch.

Note:

This sequence only applies to address errors in the reading and writing of data. In case of

an address error due to instruction fetching, if the bus cycle in which the address error

occurred is not completed by the end of step 3 above, address-error exception handling by

the CPU is restarted. This continues until the bus cycle is complete.

SH7672 Datasheet(PDF) 144 Page - Renesas Technology Corp