SH7672 datasheet(210/1292 Pages) RENESAS

210 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 184 of 1262

REJ09B0437-0100

7.4.3

CSn Space Wait Control Register (CSnWCR) (n = 0, 3 to 6)

CSnWCR specifies various wait cycles for memory access. The bit configuration of this register

varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn

space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify

CSnBCR first, then specify CSnWCR.

(1)

Normal Space, SRAM with Byte Selection

• CS0WCR

0000000000000000

R/W

0000010100000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

-----------

BAS

----

SW[1:0]

WR[3:0]

HW[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 22



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.



R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

BAS

R/W

Byte Access Selection when SRAM with Byte

Selection is Used

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read/write timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read/write access

cycle and asserts the RD/

WR signal at the write

timing.

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