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SH7672 Datasheet(PDF) 211 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 211 Page - Renesas Technology Corp |
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211 / 1292 page  Section 7 Bus State Controller (BSC) Rev. 1.00 Nov. 14, 2007 Page 185 of 1262 REJ09B0437-0100 Bit Bit Name Initial Value R/W Description 19, 18 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 All 0 R/W Reserved Set this bit to 0 when the interface for normal space or SRAM with byte selection is used. 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS0 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS0 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles |
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