SH7672 datasheet(208/1292 Pages) RENESAS

208 / 1292 page

Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 182 of 1262

REJ09B0437-0100

Bit

Bit Name

Initial

Value

R/W

Description

18 to 16

IWRRS[2:0]

011

R/W

Idle Cycles for Read-Read in the Same Space

Specify the number of idle cycles to be inserted after

the access to a memory that is connected to the

space. The target cycle is a read-read cycle of which

continuous access cycles are for the same space.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

100: 6 idle cycles inserted

101: 8 idle cycles inserted

110: 10 idle cycles inserted

111: 12 idle cycles inserted



Reserved

This bit is always read as 0. The write value should

always be 0.

14 to 12

TYPE[2:0]

000

R/W

Specify the type of memory connected to a space.

000: Normal space

001: Setting prohibited

010: Setting prohibited

011: SRAM with byte selection

100: SDRAM

101: PCMCIA

110: Setting prohibited

111: Setting prohibited

For details for memory type in each area, see table

7.2.

ENDIAN

R/W

Endian Setting

Specifies the arrangement of data in a space.

0: Arranged in big endian

1: Arranged in little endian

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